In semiconductor manufacturing, the cost of a semiconductor die generally corresponds to its size. As components in semiconductor dies become smaller, the dies themselves can shrink, and more dies can be produced from a single semiconductor wafer. Thus, the cost of die may decrease even if the smaller manufacturing process is marginally more expensive. However, some structures have a size relatively independent of the minimum feature size of the technology (or at least less dependent on minimum process dimensions than other components). Structures such as electrostatic discharge protection devices, wire bond pads, input and/or output (I/O) bond pads, I/O driver circuits, voltage regulators, capacitors, inductors, etc. may have a relatively constant size even as other components shrink.
Integrated circuit devices typically require some kind of protection against overvoltages (e.g., electrostatic discharges) that may be inadvertently applied to a terminal thereof. For example, both externally-applied DC and alternating current (AC) power sources are configured to provide a nominal power supply, or standard voltage, to an integrated circuit (IC) for its operation. On occasion, these power sources may pass to the IC transient or sustained voltages that are significantly above nominal level. In addition, human handlers and/or electronic equipment may carry or generate a significant static electrical charge, sometimes on the order of a thousand to two thousand volts or more. For example, when a human handler inadvertently touches the leads of an IC and passes such a high static charge to an input buffer on the IC, significant (and sometimes fatal) damage can be done to the IC if the IC is without some kind of protection against such ESD.
Currently, ESD protective structures may consume a substantial portion of a semiconductor die manufactured using modern manufacturing processes (e.g., 0.13 μm, 90 nm, 65 nm, etc.). Thus, these larger structures may be relatively more expensive to produce in a smaller manufacturing process than in an older manufacturing process (e.g., 0.18 μm, 0.25 etc.). Integrated circuit devices that are manufactured using advanced processes and that omit ESD and/or I/O protection structures (e.g., by offloading such structures to a die manufactured using a less advanced manufacturing process) are disclosed in U.S. patent application Ser. No. 11/505,782, filed Aug. 16, 2006, and U.S. Provisional Application No. 60/765,968, filed Feb. 7, 2006, the disclosures of which are hereby incorporated by reference.
However, wafers containing integrated circuit devices may be subject to electrostatic discharge during the manufacturing, testing, packaging, and/or assembly processes. After the integrated circuit structures have been formed on a semiconductor wafer, the wafer may be subject to ESD events during wafer sorting (e.g., testing and/or marking of each die on the wafer), bench grinding, and/or bump formation (e.g., formation of bumps for flip-chip bonding). The wafer may also be subject to ESD during the dicing step, wherein the wafer may be sawed or otherwise separated into individual semiconductor dies. Thus, it is desirable to provide ESD protection for integrated circuit device wafers during the manufacturing process without consuming valuable area on the semiconductor dies.